Objective: Design a D Flip-Flop with Async Reset.<hr>A D flip-flop is a memory element. It stores one bit of data (either 0 or 1) and can be used to synchronize and store data in sequential circuits. The <code>d</code> input represents the data to be stored, and the flip-flop, <code>dff</code>changes its state on the rising or falling edge of a <code>clk</code> signal. For this design, consider the flip-flop to be triggered during the rising edge of the <code>clk</code>. When the clock signal transitions, the <code>d</code> input is sampled, and the sampled value is stored in the flip-flop. The output <code>q</code> represents the value in the flip-flop and <code>qbar</code> is the complement of <code>q</code>. An asynchronous <code>reset</code> allows you to reset the flip-flop to a known state regardless of the clock signal's state. The reset input is asynchronous and positive edge triggered because it can be activated at any time, independent of the clock signal.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>dff</code></li><li>Inputs :<ul><li><code>d</code> : 1-bit DFF input</li><li><code>clk</code> : 1-bit clock signal</li><li><code>reset</code> : 1-bit asynchronous reset signal</li></ul></li><li>Outputs :<ul><li><code>q</code> : 1-bit DFF output</li><li><code>qbar</code> : 1-bit DFF output and complement of q output</li></ul></li></ul>

D Flip-Flop with Async Reset

&nbsp;Objective: Design a&nbsp; 4 -bit Palindrome detector circuit.<hr>A palindrome detector circuit, is used to check if a binary sequence is symmetrical, meaning it remains the same when read from left to right and right to left. Design a module <code>palindrome</code> that has a 4-bit binary input <code>a</code>. The output <code>out</code> will indicate whether the input is a palindrome or not. If the input <code>a</code> is a palindrome, then the output <code>out</code> is set to 1. If not, then the output <code>out</code> should be 0.Consider the below examples:Input: 1101 Output: 0 (not a palindrome)Input: 1001 Output: 1 (is a palindrome)<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>palindrome</code></li><li>Inputs :<ul><li><code>[3:0] a</code> : 4-bit input to accept sequence</li></ul></li><li>Outputs :<ul><li><code>out</code> : 1-bit output signal to indicate if input is a palindrome or not </li></ul></li></ul>

Palindrome Detector

Objective: Design a 2-input half subtractor<hr>A half subtractor is used to perform binary subtraction on two single bits, <code>X</code> and <code>Y</code>. It generates two outputs: the difference bit and the borrow bit . <code>X</code> and <code>Y</code> represent the minuend and subtrahend. Design a module <code>half_subtractor </code>, where the <code>Diff</code> bit represents the binary difference between X and Y. The <code>Borrow</code> bit represents whether a borrow is required from the next higher bit when subtracting Y from X.Consider the below examples:X: 0 Y: 0 Diff: 0 Borrow: 0X: 1 Y: 0 Diff: 1 Borrow: 0<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>half_subtractor</code></li><li>Inputs: <ul><li><code>X</code> : 1-bit minuend input</li><li><code>Y</code> : 1-bit subtrahend input</li></ul></li><li>Outputs: <ul><li><code>Diff</code> : 1-bit difference output</li><li><code>Borrow</code> : 1-bit borrow output</li></ul></li></ul>

Half Subtractor

Objective: Design a D Flip-Flop with Sync Reset.<hr>A D flip-flop, <code>dff</code> , is a memory element in digital logic circuits. It stores one bit of data (either 0 or 1) and can be used to synchronize and store data in sequential circuits. The <code>d</code> input represents the data to be stored, and the flip-flop changes its state on the rising or falling edge of a <code>clk</code> signal. For this design, consider the flip-flop to be triggered during the rising edge of the <code>clk</code>. When the clock signal transitions, the <code>d</code> input is sampled, and the sampled value is stored in the flip-flop. The output <code>q</code> represents the value in the flip-flop and <code>qbar</code> is the complement of <code>q</code>. A synchronous <code>reset</code> allows you to reset the flip-flop to a known state synchronized with the <code>clk</code> signal. Synchronous resets clear the flip-flop's contents in a controlled manner and ensuring that the reset operation occurs precisely at a specific clock cycle.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>dff</code></li><li>Inputs :<ul><li><code>d</code> : 1-bit DFF input</li><li><code>clk</code> : 1-bit clock signal</li><li><code>reset</code> : 1-bit synchronous reset signal</li></ul></li><li>Outputs :<ul><li><code>q</code> : 1-bit DFF output</li><li><code>qbar</code> : 1-bit DFF output and complement of q output</li></ul></li></ul>

D Flip-Flop with Sync Reset

&nbsp;Objective: Design a 2-input NAND gate.<hr>The 2-input NAND gate performs the NOT-AND operation. This means that module <code>nand_gate</code> returns a 0 (logic low) on output <code>out</code> when both inputs <code>a</code> and <code>b</code> are 1 (logic high) . The module returns a 1 (logic high) on <code>out</code> for all other input combinations of <code>a</code> and <code>b</code>.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>nand_gate</code></li><li>Inputs:<ul><li><code>a</code> : 1-bit input to NAND gate</li><li><code>b</code> : 1-bit input to NAND gate</li></ul></li><li>Outputs: <ul><li><code>out</code> : 1-bit output indicating the result of NAND operation</li></ul></li></ul>

2-input NAND gate

Objective: Design a 2-input XNOR gate<hr>The 2-input XNOR gate checks if the inputs <code>a</code> and <code>b</code> are equal. It returns a 1 on output <code>out</code> when both inputs are the same (either both 0 or both 1). The module <code>xnor_gate</code> returns a 0 at <code>out</code> when the inputs are different.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>xnor_gate</code></li><li>Inputs:<ul><li><code>a</code> : 1-bit input to XNOR gate</li><li><code>b</code> : 1-bit input to XNOR gate</li></ul></li><li>Outputs:<ul><li><code>out</code> : 1-bit output indicating the result of XNOR operation </li></ul></li></ul>

2-input XNOR gate

Objective: Design a 3-input Full Subtractor<hr>A full subtractor is used to perform binary subtraction on three binary inputs: minuend <code>X</code>, subtrahend <code>Y</code>, and a borrow input <code>Z</code>. It generates two outputs: the difference bit <code>Diff</code> and the borrow bit <code>Borrow</code>. These outputs indicate the result of subtracting <code>Y</code> and the borrow <code>Z</code> from <code>X</code>. The <code>Diff</code> bit represents the binary difference between <code>X</code> and (<code>Y</code> + <code>Z</code>).The <code>Borrow</code> bit indicates whether a borrow is required from the next higher bit when subtracting (<code>Y</code> + <code>Z</code>) from <code>X</code>.Consider the below examples:X: 0 Y: 0 Z: 0 Diff: 0 Borrow: 0X: 0 Y: 0 Z: 1 Diff: 1 Borrow: 1X: 0 Y: 1 Z: 1 Diff: 0 Borrow: 1<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>full_subtractor</code></li><li>Inputs:<ul><li><code>X</code> : 1-bit minuend input</li><li><code>Y</code> : 1-bit subtrahend input</li><li><code>Z</code> : 1-bit borrow input</li></ul></li><li>Outputs:<ul><li><code>Diff</code> : 1-bit difference output</li><li><code>Borrow</code> : 1-bit borrow output</li></ul></li></ul>

Full Subtractor

Objective: Design a 8-to-1 Multiplexer<hr>A multiplexer, often abbreviated as "mux," is a digital logic circuit that is used to select one of multiple input signals and route it to a single output. An 8:1 multiplexer is designed to take 8 input signals and select one of them as the output based on a set of select lines . Each of the 8 input lines, <code>D0, D1, D2, D3, D4, D5, D6, D7</code> carry a separate data signal. The 3 select inputs <code>Sel0, Sel1, Sel2</code>determine which one of the 8 input lines will be routed to the output <code>Out</code>.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>m81</code></li><li>Inputs:<ul><li><code>D0</code> : 1-bit data input</li><li><code>D1</code> : 1-bit data input</li><li><code>D2</code>: 1-bit data input</li><li><code>D3</code> : 1-bit data input</li><li><code>D4</code> : 1-bit data input</li><li><code>D5</code>: 1-bit data input</li><li><code>D6</code> : 1-bit data input</li><li><code>D7</code>: 1-bit data input</li><li><code>Sel0</code> : 1-bit select input</li><li><code>Sel1</code>: 1-bit select input</li><li><code>Sel2</code> : 1-bit select input</li></ul></li><li>Outputs:<ul><li><code>Out</code> : 1-bit data output determined by the select signals</li></ul></li></ul>

8-to-1 Multiplexer

Objective: Design a 1-to-4 Demultiplexer<hr>A 1:4 demultiplexer, often abbreviated as "demux," is a digital logic circuit that takes a single input signal and routes it to one of four possible output lines based on the select inputs. This input, <code>din</code>, carries the data that you want to distribute to one of the four output lines <code>y[0], y[1], y[2], y[3]</code>. The 2 select lines, <code>A[0], A[1]</code>, &nbsp;determine which of the four output lines the input will be routed to.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>Demultiplexer_1_to_4_case</code></li><li>Inputs:<ul><li><code>[1:0] A</code> : 2-bit select inputs</li><li><code>din</code> : 1-bit data input</li></ul></li><li>Outputs:<ul><li><code>[3:0] y</code> : 4-bit data output determined by the select signals </li></ul></li></ul>

1-to-4 Demultiplexer

Objective: Design a 4-to-2 priority encoder<hr>A 4:2 priority encoder is designed to encode a 4-bit binary <code>Y</code> priority value into a 2-bit binary code <code>A</code>. The priority encoder identifies the highest-priority active input and produces a binary output code <code>A</code> representing that priority. There are four input lines labeled as <code>Y[0], Y[1], Y[2], Y[3]</code>. These input lines represent the priority value, where <code>Y[0]</code> is the lowest priority, and <code>Y[3]</code> is the highest priority. Consider the examples -&nbsp;Y=0100 A=10Y=0010 A=01Y=0001 A=00Y=1010 A=11<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>priority_encoder</code></li><li>Inputs:<ul><li><code>[3:0] Y</code> : 4-bit binary input</li></ul></li><li>Outputs:<ul><li><code>[1:0] A</code> : 2-bit binary priority encoded output</li></ul></li></ul>

4-to-2 priority encoder

Objective: Design and code a SR flip-flop<hr>An SR flip-flop <code>srff</code> is a bistable sequential circuit with two inputs: <code>S</code> (Set) and <code>R</code> (Reset). The two stable states are '0' and '1' . SR flip-flop with synchronous behavior is controlled by a clock signal <code>clk</code> . The <code>S</code> and <code>R</code> inputs control the output state of the flip-flop according to the set and reset conditions. If both inputs are low, the flip-flop maintains its current state. This design does not require considering a reset signal.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>srff</code></li><li>Inputs:<ul><li><code>s</code> : 1-bit Set input</li><li><code>r</code> : 1-bit Reset input</li><li><code>clk</code> : 1-bit Clock input</li></ul></li><li>Outputs:<ul><li><code>q</code> : 1-bit SRFF output</li><li><code>qbar</code> : 1-bit SRFF output which is the complement of <code>q</code></li></ul></li></ul>

SR Flip-Flop

Objective: Generate the Fibonacci Series of numbers - 0, 1, 1, 2, 3, 5, 8, 13, etc.<hr>A Fibonacci series is a sequence of numbers in which each number is the sum of the two preceding ones. Design a module <code>fibonacci</code> that starts with the first two numbers as 0, and 1 on reset and the next number in the sequence is the <code>sum</code> of the first two.&nbsp; Use an <code>enable</code> signal to control if the circuit should advance and calculate the next number in the sequence (if <code>enable</code> is 1) , or hold its previous value (if <code>enable</code> is 0) . Use a <code>clk</code> signal and active low async reset <code>rst</code>.Consider the examples -&nbsp;<code>clk</code> = 0, <code>rst</code> = 1, <code>enable</code> = 0, <code>sum</code> = 0<code>clk</code> = 1, <code>rst</code> = 1, <code>enable</code> = 0, <code>sum</code> = 0<code>clk</code> = 0, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 0<code>clk</code> = 1, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 1<code>clk</code> = 0, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 1<code>clk</code> = 1, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 2<code>clk</code> = 0, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 2<code>clk</code> = 1, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 3<code>clk</code> = 0, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 3<code>clk</code> = 1, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 5<code>clk</code> = 0, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 5<code>clk</code> = 1, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 8<code>clk</code> = 0, <code>rst</code> = 1, <code>enable</code> = 1, <code>sum</code> = 8<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>fibonacci</code></li><li>Inputs:<ul><li><code>clk</code> : 1-bit clock signal</li><li><code>rst</code> : 1-bit active low async reset signal</li><li><code>enable</code> : 1-bit enable control</li></ul></li><li>Outputs:<ul><li><code>[8:0] sum</code> : 9-bit Fibonacci series output</li></ul></li></ul>

Fibonacci Series

Objective: Design and code a 4-bit binary to gray code converter.<hr>Gray code, also known as reflected binary code, is a binary numeral system in which two successive values differ in only one bit position. A binary-to-Gray code converter is designed to take a binary input <code>bin</code> , and convert it into Gray code <code>G</code> .&nbsp;Consider the examples -&nbsp;Binary Code: 0001 Gray Code: 0001Binary Code: 0010 Gray Code: 0011Binary Code: 0011 Gray Code: 0010Binary Code: 0100 Gray Code: 0110<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>bin2gray</code></li><li>Inputs:<ul><li><code>[3:0] bin</code> : 4-bit Binary code input</li></ul></li><li>Outputs:<ul><li><code>[3:0] G</code> : 4-bit Gray code output</li></ul></li></ul>

Binary-to-Gray Code Converter

Objective: Design and code a 4-bit Gray to Binary code converter.<hr>A Gray-to-Binary code converter module <code>gray2bin</code> is designed to take a Gray code input <code>G</code> and convert it into binary code <code>bin</code> . Gray code, also known as reflected binary code, is a binary numeral system in which two successive values differ in only one bit position. By converting Gray code to binary code, you obtain a more conventional binary representation of the same value.Consider the examples -&nbsp;Gray Code: 0001 Binary Code: 0001Gray Code: 0011 Binary Code: 0010Gray Code: 0010 Binary Code: 0011Gray Code: 0110 Binary Code: 0100<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>gray2bin</code></li><li>Inputs:<ul><li><code>[3:0] G</code> : 4-bit Gray code input</li></ul></li><li>Outputs:<ul><li><code>[3:0] bin</code> : 4-bit Binary code output</li></ul></li></ul>

Gray-to-Binary Code Converter

Objective: Design and code a 4-bit FIFO of depth 16 with Overflow/Underflow conditions<hr>Design a 16 Deep FIFO module <code>fifo_mem</code> of 8 bits width. The FIFO has a 8 bit input <code>data_in</code> with <code>wr</code> and <code>rd</code> control signals to indicate write enable and read enable. When <code>wr</code> is asserted with <code>data_in</code>, the FIFO is populated with the input <code>data_in</code>. When <code>rd</code> is asserted, at <code>clk</code> the output <code>data_out</code> reads out the FIFO value. Use status signals <code>fifo_full</code> and <code>fifo_empty</code> to indicate Full and Empty conditions of FIFO. <code>fifo_overflow</code> indicates when the FIFO is full and data is still being written into the FIFO. <code>fifo_underflow</code> is used to say the FIFO is empty and data is still being read out.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>fifo_mem</code></li><li>Inputs:<ul><li><code>wr</code> : 1-bit Write enable input</li><li><code>rd</code> : 1-bit Read enable input</li><li><code>clk</code> : 1-bit Clock input</li><li><code>rst_n</code> : 1-bit active low reset input</li><li><code>[7:0] data_in</code> : 8-bit Binary data input to FIFO</li></ul></li><li>Outputs:<ul><li><code>[7:0] data_out</code> : 8-bit Binary data output from FIFO</li><li><code>fifo_full</code> : 1-bit FIFO full indication output</li><li><code>fifo_empty</code> : 1-bit FIFO empty indication output</li><li><code>fifo_overflow</code> : 1-bit FIFO overflow indication output</li><li><code>fifo_underflow</code> : 1-bit FIFO underflow indication output</li></ul></li></ul>

FIFO with Overflow/Underflow

Objective: Design a Clock Divider to divide the input clock by 2.<hr>A clock divider is used to reduce the frequency of an input clock signal <code>clk</code> by a specific factor. In this case, we want to divide the input clock frequency by 2, which effectively generates an output clock signal <code>out_clk</code> with half the frequency of the input. To achieve a division by 2, you need to create logic that toggles the output state of the <code>out_clk</code> signal with every rising or falling edge of the input clock <code>clk</code>. Use an active low reset signal <code>rst</code> in the design.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>frequency_divider_by2</code></li><li>Inputs:<ul><li><code>rst</code> : 1-bit reset input</li><li><code>clk</code> : 1-bit Clock input</li></ul></li><li>Outputs:<ul><li><code>out_clk</code>: 1-bit divided clock output</li></ul></li></ul>

Clock Divider by 2

Objective: Design a Clock Divider to divide the input clock by 4.<hr>A clock divider is used to reduce the frequency of an input clock signal <code>clk</code> by a specific factor. In this case, we want to divide the input clock frequency by 4, which effectively generates an output clock signal <code>clk_out</code> with one-fourth the frequency of the input. To achieve a division by 4, you need to create logic that generates a pulse for every fourth rising edge of the input clock <code>clk</code>. Use an active high reset signal <code>rst</code> in the design.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>frequency_divider_by4</code></li><li>Inputs:<ul><li><code>rst</code> : 1-bit reset input</li><li><code>clk</code> : 1-bit Clock input</li></ul></li><li>Outputs:<ul><li><code>clk_out</code>: 1-bit divided clock output</li></ul></li></ul>

Clock Divider by 4

Objective: Design a Clock Divider to divide the input clock by 3.<hr>A clock divider is used to reduce the frequency of an input clock signal <code>clk</code> by a specific factor. In this case, we want to divide the input clock frequency by 3, which effectively generates an output clock signal <code>clk_out</code> with one-third the frequency of the input. To achieve a division by 3, you need to create logic that generates a pulse <code>clk_out</code>for every third rising edge of the input clock <code>clk</code>. Use an active high reset signal <code>reset</code> in the design.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>clk_div3</code></li><li>Inputs:<ul><li><code>reset</code> : 1-bit active high reset input</li><li><code>clk</code> : 1-bit Clock input</li></ul></li><li>Outputs:<ul><li><code>clk_out</code>: 1-bit divided clock output</li></ul></li></ul>

Clock Divider by 3

Objective: Design a Clock Divider to divide the input clock by 4.5.<hr>A clock divider is used to reduce the frequency of an input clock signal by a specific factor. In this case, we want to divide the input clock frequency <code>clk </code>by 4.5, which effectively generates an output clock signal <code>clk_out</code> with 1/4.5 the frequency of the input. Dividing the clock by 4.5 is challenging because it's not a straightforward integer division. One common way to approximate this division is to create a clock signal that toggles its state with each rising edge of the input clock <code>clk</code> and then generates additional pulses to approximate the 0.5 division. You can create a 4x division using flip-flops and then generate extra pulses to simulate the 0.5x division. Use an active high reset signal <code>reset</code> in the design.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>clk_div45</code></li><li>Inputs:<ul><li><code>reset</code> : 1-bit active high reset input</li><li><code>clk</code> : 1-bit Clock input</li></ul></li><li>Outputs:<ul><li><code>clk_out</code>: 1-bit divided clock output</li></ul></li></ul>

Clock Divider by 4.5

Objective: Design a 4-bit Up/down counter with an asynchronous reset<hr>An up/down counter <code>up_down_counter</code> is a sequential circuit that can count upwards or downwards based on control inputs. An asynchronous active high <code>reset</code> allows you to reset the counter at any point in time, regardless of the clock <code>clk</code>. When the <code>reset</code> signal is asserted, the <code>counter</code> should be cleared. Implement the counting logic based on the counting direction control signal <code>up_down</code>. For an up/down counter, you'll need to add logic for both up and down counting. If <code>up_down</code> is 0, the counter will count in ascending order. If <code>up_down</code> is 1, the counter will progress in a descending order. The counter will wrap around on hitting the highest or lowest count.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>up_down_counter</code></li><li>Inputs :<ul><li><code>up_down</code>: 1-bit up/down input</li><li><code>clk</code> : 1-bit clock signal</li><li><code>reset</code> : 1-bit asynchronous active high reset signal</li></ul></li><li>Outputs :<ul><li><code>[3:0]counter</code> : 4-bit counter output</li></ul></li></ul>

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